1. Field
Various embodiments of the present invention relate to a memory device and a memory system including the same.
2. Description of the Related Art
A memory device includes a plurality of memory cells. A memory cell may include a transistor serving as a switch and a capacitor for storing electric charges corresponding to data. Data stored in the capacitor of the memory cell is determined according to the amount of charge stored in the capacitor. When the charge is large, the corresponding memory cell is determined to store high data (logic 1). When the electric charges are discharged, the corresponding memory cell is determined to store low data (logic 0).
Since data is retained in the form of a charge in a capacitor, in principle no power is consumed. However, since the initial electric charge is lost to leakage current through a PN junction of an MOS transistor or the like, data may be lost. In order to prevent such data loss, the data stored in the memory cell is to be read before the data is lost, and the capacitor is to be recharged according to the read information. Such a recharging operation, which is referred to as a refresh operation, needs to be periodically repeated to retain the data.
A refresh operation is performed whenever a refresh command is inputted to a memory device from a memory controller. The memory controller inputs the refresh command to the memory at each predetermined time in consideration of the data retention time of the memory device. The data retention time may indicate a time during which data of a memory cell may be retained without a refresh operation. Since memory cells included in a memory device are designed to have a data retention time which is equal to or longer than a preset reference time, an interval between the refresh operations may be determined in consideration of the reference time.
However, when some memory cells have data retention time that is less than the reference time, due to internal or external factors, data of the memory cells may be degraded or lost. Internal factors include memory cell defects. Examples of internal factors include capacitors of the memory cells having relatively low capacitance or transistors having a large amount of leakage current. Furthermore, external factors include the influence of active-precharge operations of neighboring word lines.
FIG. 1 illustrates a cell array included in a memory device. In FIG. 1, ‘BL’s represent bit lines.
Referring to FIG. 1, WLK−1, WLK, and WLK+1 represent three word lines successively arranged in parallel, WLK with ATTACK_WL represents a highly active word line of which the number of activations or active frequency is high, or of which the active time is long. WLK−1 and WLK+1 represent adjacent word lines arranged adjacent to the highly active word line WLK. Furthermore, CELL_K−1, CELL_K, and CELL_K+1 represent memory cells coupled to the word lines WLK−1, WLK, and WLK+1, respectively. The memory cells CELL_K−1, CELL_K, and CELL_K+1 include cell transistors TR_K−1, TR_K, and TR_K+1 and cell capacitors CAP_K−1, CAP_K, and CAP_K+1, respectively.
In FIG. 1, when the word line WLK is activated a large number of times, activated at a high frequency, or activated for a long time, the voltage of the word line WLK may be frequently toggled or maintained at a high voltage for a long time, thereby influencing data stored in the memory cells CELL_K−1 and CELL_K+1 coupled to the adjacent word lines WLK−1 and WLK+1 due to couplings between the highly active word line WLK and the adjacent word lines WLK−1 and WLK+1. Such influence may reduce data retention time.